LIBRARY ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;

entity lab31 is
    port (Di :in std_logic;
    clk :in std_logic;
    rst :in std_logic;
    strobi :in std_logic;
    Do :out std_logic );
end lab31;

architecture beh of lab31 is
    signal count: unsigned(8 downto 0);
    signal strob, data: std_logic;
begin
    process (clk, rst)
    begin
        if (rst = '1') then
            count <= "000000000";
            data<='0';
        elsif (clk = '1' and clk'event)then
            count <= count+1;
            if (strob='1')then
                data<=Di;
            end if;
        end if;
    end process; 
    strob<='1' when count=511 else
    '0'; 
    do <=(count(8) xor data) and count(4);
end beh;

 